International Journal of Students' Research in Technology & Management, Vol 3 (2) February 2015
(Papers were presented during Online Research Conference 'CONFLUENCE' on 23rd January 2015)
1. Energy Conservation in Households in Urban Areas in India
Aashee Garg and Anusha Agarwal
Abstract: India, as a country is very rich in terms of natural resources however as citizens, we have not respected this fact and have been continuously exploiting nature’s gift to mankind. Further as the population is ever increasing, the load on the consumption of resources is unprecedented. This has led to the depletion of natural resources such as coal, oil, gas etc., apart from the pollution it causes.
It is time that we shift from use of these conventional resources to more effective new ways of energy generation. We should develop and encourage usage of renewable resources such as wind and solar in households to conserve energy in place of the mentioned nonrenewable energy sources. This paper deals with the most effective ways in which the households in India can conserve energy thus reducing effect on environment and depletion of limited resources.
Key words: Energy Consumption, Resources, India, Renewable Resources and Environment.
2. Human Computer Interface for Victims using FPGA
M.S.Heetha, M.Shenbagapriya, and M.Bharanidharan
Abstract: Visually impaired people face many challenges in the society; particularly students with visual impairments face unique challenges in the education environment. They struggle a lot to access the information, so to resolve this obstacle in reading and to allow the visually impaired students to fully access and participate in the curriculum with the greatest possible level of independence, a Braille transliteration system using VLSI is designed. Here Braille input is given to FPGA Virtex-4 kit via Braille keyboard.
The Braille language is converted into English language by decoding logic in VHDL/Verilog and then the corresponding alphabet letter is converted into speech signal with the help of the algorithm. Speaker is used for the voice output. This project allows the visually impaired people to get literate also the person can get a conformation about what is being typed, every time that character is being pressed, this prevents the occurrence of mistakes.
Keywords: FPGA, Braille keyboard, Visually Impaired People, VHDL, Text to speech.
3. Modelling and Simulation of Solar PV Array Field Incorporated with Solar Irradiance and Temperature Variation to Estimate Output Power of Solar PV Field
Vishwesh Kamble, Milind Marathe, and Rahul Rane
Abstract: Photovoltaic systems are designed to feed either to grid or direct consumption. Due to global concerns, significant growth is being observed in Grid connected solar PV Plants. Since the PV module generates DC power, inverter is needed to interface it with grid. The power generated by a solar PV module depends on surrounding such as irradiance and temperature.
This paper presents modelling of solar PV arrays connected to grid-connected plant incorporated with irradiance and temperature variation, to design simulator to study and analyse effect on output power of solar PV arrays with irradiance and temperature variation, also to estimate the output power generated by PV arrays. The mathematical model is designed implemented separately on simulator for each PV components connected in PV systems, which are PV cell, Module, sting, array and field of arrays. The results from simulation based on model are verified by the data collected from power plants and experiments done on solar PV cell.
Keywords— Photovoltaic, Irradiance, Temperature, Array, Model, Simulator
4. A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique
R.Mohanapriya, and K. Rajesh
Abstract: High speed and low power Multiplier and Accumulator (MAC) unit is at most requirement of today’s VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture, Radix-4 Modified Booth Encoding (MBE) is used to produce the partial products. In this multiplication and accumulation has been combined using a hybrid type of Carry Save Adder (CSA). So the performance will be improved.
A Carry Look ahead Adder is inserted in the CSA tree to reduce the number of bits in the final adder. In booth multiplication, when two numbers are multiplied some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose Spurious Power Suppression Technique (SPST) is used to remove useless portion of the data in addition process. In this modified architecture, the overall process is three stages to produce the result. The modified MAC operation is coded with Verilog and simulated using Xilinx 12.1.
Keywords: DSP, MAC, Radix-4, Modified Booth Encoding, CSA, CLA, SPST, Verilog.
5. An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator
N.Nithya, M.Chandraman and S.Veerakumar
Abstract: A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories.
The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high. Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.
Keywords: Logic Built In Self-Test (BIST), Fault diagnosis, Bit Swapping-Linear Feedback Shift Register(BS-LFSR),Data Encryption Standard (DES),Test Pattern Generation.
6. 3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor
K. Suresh Kumar, S. Anitha and M. Gayathri
Abstract: In this model a runtime cache data mapping is discussed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The suggested method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows energy reduction achieving up to 22.88% compared to an existing solution which considers only the temperature distribution. New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation high performance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs with energy reduction achieving up to 19.55% by supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility.
Keywords: MPSoC, HPC, CMP, Interconnect, TSV, Cache Management.